Events sometimes occur which disrupt the normal sequence of instruction. These are called exceptions and interrupts. Intel defines exceptions in relation to an unsuccessful attempt to execute an instruction. Interrupts are defined as a hardware response to a event unrelated to program execution.
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# TYPE B/C ERR SOURCE CAUSE
HEX CODE
0 Fault C No Divide Overflow ( perhaps by zero )
1 DR6 B No Debug Exception
2 Int B No NMI ( Non-Maskable Interrupt ), normally
hardware fault
3 Trap B No Breakpoint ( INT 3 instruction )
4 Trap B No Overflow ( INTO instruction )
5 Fault B No Bounds Check ( BOUND instruction )
6 Fault B No Invalid Opcode
7 Fault B No Coprocessor not available, see note
8 Abort Abort Always Double Fault, any instruction
Zero
9 Fault C Yes Coprocessor Segment Overrun (286,386
only) (Fault D in 486+)
A Fault C Yes Invalid TSS
B Fault C Yes Segment Not Present ( swapped out )
C Fault C Yes Stack Exception
D Fault C Yes General Protection
E Fault PF Yes Page Fault ( paged out )
F ( reserved )
10 Fault B No Coprocessor Error
11 Fault ? Always Alignment Check
Zero
12 Abort ?? Machine
Check
13-1F ( reserved )
20-FF Trap N/A No Available for Hardware Interrupts Via
'INTR' Pin
00-FF Trap N/A No The INT instruction is actually a trap.
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Note: Co-processor not available may be due to not having one, or because the content of the co-processor belongs to another thread. The co-processor data needs to be saved and restored only when more than one thread is using it. Bit 3 in CR0 indicates that a thread switch has occurred and will cause a trap 7 when a co-processor instruction is decoded.
Explanation of B/C column B - Benign, means it is ok with any other exception C - Contributary, means it will contribute to a double fault PF - Page Fault, means a referenced address is not present